A task mapping approach with reliability considerations for multicore systems based on wireless network-on-chip

Abstract

ABSTRACT: Wireless Network-On-Chip (WNoC) paradigm has been proposed to increase the performance in future generations of Multi-Processor System-on-Chip (MPSoC) with hundreds/thousands of processing elements (PEs). For such platforms, efficient task mapping techniques are required to improve latency, communication cost, execution time, and other relevant metrics. Moreover, as the increasing complexity in MPSoC designs and applications has led to increasing the probability of failures in the system components, the mapping technique must incorporate strategies to cope with resource failures. In the literature, plenty of techniques have been employed for task mapping in NoCs, but just a few are reported for WNoCs. Therefore, in this work, we propose a new hybrid approach for the mapping of tasks called Rectangular Virtual Regions PBIL for WNoCs (RVRP-WNoC) that works at both design-time and run-time. At design-time, RVRP-WNoC determines multiple pre-mappings for each application, while at run-time, RVRP-WNoC uses these pre-mappings to map applications requested for execution based on current operating conditions, employing wireless links available in WNoC when possible. Also, the proposed technique incorporates a procedure to isolate faulty resources during the mapping of tasks to keep the system alive as much as possible, even at the expense of performance degradation. We evaluated the performance of the proposed approach against a set of heuristic techniques. The results demonstrated that RVRP-WNoC delivered better solutions compared to other approaches, improving metrics such as latency, execution time, and mapping span time by 62%, 37%, and 29% on average, respectively.