NoC Performance Estimation tool based on formal models for Scientific Applications

Abstract

ABSTRACT : As the number of Processing Elements (PEs) present in Systems-on-Chip (SoC) increases, the complexity of the applications running in these systems increases as well. A Network-on-Chip (NoC) provides the communication channels between the PEs, and its proper design is a decisive factor in meeting the performance requirements of an SoC application. However, NoC design is a complex task that involves the exploration of a wide design space involving subjects as NoC topology and application mapping. During the design process, a system architect explores several NoC configurations, trying to find a system prototype that meets the performance requirements of an application. This is done using detailed simulations of the hardware and software of the system (known as cycle-accurate simulations), and in general, they are very time-consuming to run. On the other side of the spectrum, high-level simulations of a system are faster to run, but due to the simplicity of their models, their estimations can be inaccurate. Thus, a tool capable of fast execution and accurate NoC performance estimations is of interest. In this thesis, an NoC performance estimation tool based on a formal model is proposed. This tool uses a recently released state-of-the-art traffic suite to model traffic patterns of several scientific applications running in an NoC. This differentiates the tool proposed in this thesis from similar tools reported in the literature, that can only model synthetic traffic patterns and thus, their performance estimations are of limited use. With the ability of modeling traffic patterns of real applications, the NoC performance estimations made by the proposed tool are similar to the ones obtained from a cycle-accurate simulation. Additionally, it will be shown that the tool proposed in this thesis runs faster than a cycle-accurate simulator, which makes it ideal for design space exploration at the early stages of system development.